If we remember that manufacturing cost is the first of the "Four Horsemen" of vertical integration, this story is especially compelling. The high cost of TSVs has been a barrier to adoption, but we're making significant progress. Three years ago, the calculated total cost of ownership for a 10K wafer start fab was running $320/wafer. The 2010/2011 target for the international Semiconductor 3-D Equipment and Materials Consortium (EMC-3D) is $120/wafer.
Because I can't post without a couple of cool quotes, I wanted to highlight that:
"Mass production of 3-D TSVs has already started in MEMS and CMOS image sensors, power applications are just beginning, and stacked DRAM modules are on track for 2010–2011."and, most importantly:
"The level of activity in TSV suggests the performance improvements and cost reductions have combined to enable financial justification by many companies to begin aggressive development. Continued reduction of cost will increase the speed of adoption. Currently, the consortium sees at least 15 companies with TSV research or pilot production, and we expect many more to be added in 2010."Clearly, 2010 is the year of commercial exploitation of TSVs for vertical integration.
Because I love illustrations, I wanted to close with this nice picture from the story. It shows a 3-D stack that [they suggest] closely resembles commercial chips of the future. It consists of a 25 µm thick logic die, with a commercial DRAM stacked on top, using TSVs and microbumps. (Source: IMEC)