The cover story in Semiconductor International's February 2010 issue is Driving Down the Cost of TSVs. The story provides good insight into the progress towards reducing the cost of the entire TSV process flow.
A very good overview of the current state of TSV technology came out today on the IEEE Spectrum site. The whole piece is well worth a read, and I strongly encourage everyone with an interest in the subject to check it out. The first illustration is priceless
I came across this excellent slide deck titled Through Silicon Vias (TSV): Design and Reliability (PDF) from our friends at ALLVIA, the TSV foundry specialists.
The IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter is putting together what promises to be an extremely interesting program titled, "3D IC Integration: The Next Generation of Electronics." The fun will commence at 6:00 PM on Wednesday, March 10, 2010, in Santa Clara.
For those, like me, that don't cast our info nets nearly wide enough, this event might have escaped our attention. That is unfortunate. The 26th Annual Thermal Measurement, Modeling and Management Symposium is being held next week in Santa Clara. One course, "Cooling Challenges in 3D Packaging" is of particular interest to those who follow this humble blog. The short course will be presented by Dereje Agonafer, Ph.D. Dr. Agonafer is a Professor and Director, Elec, MEMS & Nanoelectronics Systems Packaging Center at the University of Texas at Arlington (Faculty profile).
I'm really mad at myself for not heading up to the ISSCC this year. The conference featured a full day forum on 3D Integration. Although I'm sorry that I missed it, I'm thrilled by the attention, as it clearly demonstrates just how important this technology is becoming. I was particularly gratified to see a good mix of industry and academic interests involved in the 3D forum.
The International Solid-State Circuits Conference (ISSCC) is currently underway in San Francisco. As has been the case for as long as I can remember, the attendees are apparently (I couldn't swing attending the conference) discussing the end of the world as we know it. Variously referred to as the end of silicon scaling, the end of CMOS viability and the end of Moore's law, the premise is always the same. At xx node, silicon just won't work anymore. Generally I just let this conversation flow over me, but one story in EETimes caught my eye.
Thanks to a much appreciated intervention by Dr. Prasad Chaparala, the event chairman, I was able to attend the IEEE SCV EDS Symposium: 3D Interconnect - Shaping Future Technology after all. It was fantastic! The information and insight were priceless. I've started preparing a series of posts covering the event, of which this will be the first.
EETimes had a great article covering the exciting developments at NuPGA (Their site is currently "Under Construction" — Hopefully more will come, soon).